Many digital circuits receive a clock signal to operate. One type of circuit that receives a clock signal to operate is a memory circuit, such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM). In a memory circuit operating at high frequencies, it is important to have a clock signal that has about a 50% duty cycle. This provides the memory circuit with approximately an equal amount of time on the high level phase and the low level phase of a clock cycle for transferring data, such as latching rising edge data and latching falling edge data into and out of the memory circuit.
Typically, a clock signal is provided by an oscillator, such as a crystal oscillator, and clock circuitry. The oscillator and clock circuitry often provide a clock signal that does not have a 50% duty cycle. For example, the clock signal may have a 45% duty cycle, where the high level phase is 45% of one clock cycle and the low level phase is the remaining 55% of the clock cycle. To correct or change the duty cycle of a clock signal, a duty cycle corrector provides signals with transitions separated by substantially one half of a clock cycle.
Typically, analog and digital duty cycle correctors receive many clock cycles to achieve duty cycle correction. In analog duty cycle correctors, it is difficult to keep accumulated charges for an extended length of time. Even in power saving mode, clock signals are provided to the analog duty cycle corrector to update the accumulated charges. Thus, even in power saving mode, the analog duty cycle corrector remains operable and clock buffers remain enabled, which continuously consumes power. In digital duty cycle correctors, fine delay units are difficult to make and complex control logic is needed to increase correction speed.
For these and other reasons there is a need for the present invention.